1. Field of the Invention
The present invention relates to a programmable one-board computer, and methods of verification of a logic circuit and of alteration to an actual circuit using the programmable one-board computer being capable of accepting varieties of systems and of accepting alterations of those systems quickly with ease by making use of internal circuit of programmable logic devices (PLD) of which are erasable/reconfigurable.
2. Description of the Prior Art
In a prior one-board computer, there are disposed on a system board 16, as illustrated in FIG. 12 for example, a chip 10 of a central microprocessor, varieties of general purpose ICs 12 (such as TTLs, RAMS, ROMS, etc.), and a peripheral circuit composed of a very small number of programmable logic devices (PLD) 14 for use in decoding of any addresses.
It is impossible to reconfigure the prior one-board computer to another circuit for other applications after having once been assembled.
Additionally, when a newly designed logic circuit is altered to an actual circuit on the one-board computer, it can not utilized any data of the prior one-board computer which is design property. A new design must be done from the beginning each time a newly designed logic circuit is needed.
Further, an LSI (large scale integrated) circuit includes many constituent parts with complicated relations thereamong. Therefore, a designer can predict all results in each design process. Moreover, even in a prototype process of such a design, any wrong design results in very high costs. For reducing the possibility of such design error there has been an increase in demand for a computer tool which a designer can analyze and verify a designed circuit prior to expensive manufacture of silicon devices.
The prior practice to design an IC is as follows:
1) the step of an abstract idea in designers thoughts, PA0 2) the step of architecture specifications (register transfer level (RTL)) that is, for example, a combination of black boxes, PA0 3) the step of a schematic logical design (gate level) that is, for example, a combination of circuit blocks, PA0 4) the step of a circuit design (transistor level) that is a combination of transistor circuits, and PA0 5) the step of a mask layout on silicon wafers.
The practice also includes the step of a design on testing of any fault of a finished product.
Accordingly, in order to design a large-scale system and realize it with a combination of actual large scale integrated circuit, the verification is very important to cheek whether or not the design is proper.
For the prior verifications works, there are also various design steps. In the first step, where the abstract idea is existent in designer's thoughts, a designer performs the verification in his thoughts. Then, in the successive RTL level, the designer likewise performs the verification in his thoughts or performs functional simulation through a logic simulator with the aid of a computer. Also in the successive gate level, the designer performs functional simulation through a logic simulator with the aid of a computer. In the next transistor level, a timing analysis is performed through a timing simulator with the aid of a computer. Additionally, in the mask layout step, a circuit is extracted from the mask data using a computer for which a timing analysis is computed through a timing simulator. Furthermore, for the final step of testing, fault simulation is performed through a fault simulator using test vectors (test Patterns). The test vectors are prepared by the designer with the aid of a computer.
In the prior verifications, however, a design circuit (design data) 20 is modeled in a computer 24, and the computer 24 evaluates the simulated resulting model 26. Therefore, for the logic simulation of 10000 gates, for example, which is performed by a 1MIPS machine, verification thereof requires the time exceeding one hour. For logic simulation beyond a transistor level, verification requires much more time. Additionally, since a designer 22 inputs a design circuit 20 into the computer 24 in the form of a model, wrong verifications will likely happen. Further, timing do not satisfactorily correspond to actual situations.
In order to estimate whether a test vector for verification is adequate or not, it is necessary to intentionally produce internal failures such as element failure or disconnection failure at various portions of a modeled logic circuit for examination of a failure detection rate by the test vector. In a circuit for which no failure detection is taken into consideration, the rate might be 70% or less in a simple failure, and in a circuit where failure detection is taken into consideration, the rate is about 95% or more in a similar simple failure. However, in a system where failures are produced one by one at each portion of a modeled logic circuit, each test vector is generated by computation, and it is necessary to repeat computation for each failure. Therefore, even through a test vector operation that takes about three seconds, accurate estimate of a failure detection rate takes about a week.
Additionally, obtaining an output pattern as a reference for comparison when an input pattern for a device under testing (DUT input pattern) is inputted into the device, similar required computation takes a long period of time.
Alternatively, another known technique is disclosed in Japanese Laid-Open Publication Nos. 62-93736 and 63-157072. Instead of using the software simulator to check a operation of an LSI circuit, the hardware simulator is prepared by specifying a necessary integrated circuit module and writing code data corresponding to logic specifications into a PLD of the specified integrated circuit module.
The hardware simulator, however, includes ICs arranged regularly such as PLDS, EPROMS, and RAMS, etc., into which varieties of serial IC modules can be optionally incorporated. Many other IC modules that might be unnecessary depending upon the associated logic circuit results in a complicated structure thereof.